Electrical engineering



Problem1:Ignoringlambda for the moment (lambda = 0 here), what must the widths of thePMOS and NMOS transistor be? You can assume all devices aresaturated.


Atsaturation, λ = 0 (no channel length modulation)


ForP-channel, ISD=0.5µpCOXW/L(VSG-|VT|)2(1+λ VSD),




ForN-channel ISD=0.5µNCOXW/L(VSG-VT)2(1+ λ VDS).


IDS=100µA,W= 21µM.

Problem2:&nbspWhatDC bias voltage do you need at the input of transistor 1?

DCbias voltage= VDD/2=2.5/2=1.25V.

Problem3:&nbspWhatis the small signal voltage gain, vo/vin,&nbspofthis circuit?

Hereyou will need the output conductance with lambda having the values inthe table.

Ids= Vds/R,R= Vds/Ids,Vdd&nbspis2.5V. RD=2.5/(100µA)=25K.


Therefore,2.5-42*10^-6*(0.2)*25000= 2.29V.

Maxvoltage gain AV=IDRD/(VOV/2)=2.29/(2.5/2)=1.832.

Problem4:&nbspWhatis the small signal output resistance, Ro,at vout&nbsplookingback into the circuit?

Hereyou will need the output conductance with lambda having the values inthe table.

Ro=1/(λ ID),VD=VDD-IDRD=2.5-2.29=0.21V

ID=VD/RD=0.21/25K= 8.4µA

ThereforeRo=1/(0.17*8.4µA)= 700.3MΩ

Problem5:&nbspIfyou double the bias current, does the small signal gain increase,decrease or stay the same? The gate overdrive voltage, VGS-VT,remains 0.2V for all devices. Hint: How does trans conductance andoutput conductance depend on bias current?

Thesmall signal gain will stay the same since from the followingrelationship

Thetransconductance varies directly proportional to the input current asthere will b a decrease in the resistance.


Croon,J. A., Sansen, W. M. C., &amp Maes, H. E. (2005). Matchingproperties of deep sub-micron

MOStransistors.New York: Springer.

Maricau,E., &amp Gielen, G. (2013). AnalogIC reliability in nanometer CMOS.New York, NY: Springer.

BiasTemperature Instability for Devices and Circuits.(2014). New York, NY: Springer New York.

Kuon,I., &amp Rose, J. (2010). Quantifyingand Exploring the Gap Between FPGAs and ASICs.Boston, MA: Springer-Verlag US.